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1

An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch

Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik

Journal:

Journal of Electronic Testing

Year:

2002

Language:

english

File:

PDF, 167 KB

english, 2002

2

Expert system to configure global design for testability structure in a VLSI circuit

Sudipta Bhawmik, Parimal Palchaudhuri

Journal:

Microprocessors and Microsystems

Year:

1989

Language:

english

File:

PDF, 955 KB

english, 1989

3

KIDLAN: A hardware description language

Anurag Acharya, Sudipta Bhawmik, C.R.K. Prasad, P. Palchaudhuri

Journal:

Microprocessing and Microprogramming

Year:

1989

Language:

english

File:

PDF, 919 KB

english, 1989

4

Integration of partial scan and built-in self-test

Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik

Journal:

Journal of Electronic Testing

Year:

1995

Language:

english

File:

PDF, 1.15 MB

english, 1995

5

Selecting test methodologies for PLAs and random logic modules in VLSI circuits — an expert systems approach

Sudipta Bhawmik, V.K. Narang, Parimal Pal Chaudhuri

Journal:

Integration, the VLSI Journal

Year:

1989

Language:

english

File:

PDF, 754 KB

english, 1989

6

[IEEE 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - New York City, NY, USA (2013.10.2-2013.10.4)] 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - Impact of mid-bond testing in 3D stacked ICs

Taouil, Mottaqiallah, Hamdioui, Said, Marinissen, Erik Jan, Bhawmik, Sudipta

Year:

2013

Language:

english

File:

PDF, 247 KB

english, 2013

7

[IEEE 2014 IEEE 32nd VLSI Test Symposium (VTS) - Napa, CA, USA (2014.04.13-2014.04.17)] 2014 IEEE 32nd VLSI Test Symposium (VTS) - At-speed interconnect testing and test-path optimization for 2.5D ICs

Wang, Ran, Chakrabarty, Krishnendu, Bhawmik, Sudipta

Year:

2014

Language:

english

File:

PDF, 833 KB

english, 2014

8

[IEEE 2014 32nd IEEE International Conference on Computer Design (ICCD) - Seoul, South Korea (2014.10.19-2014.10.22)] 2014 IEEE 32nd International Conference on Computer Design (ICCD) - Built-in self-test for interposer-based 2.5D ICs

Wang, Ran, Chakrabarty, Krishnendu, Bhawmik, Sudipta

Year:

2014

Language:

english

File:

PDF, 1.32 MB

english, 2014

9

Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs

Wang, Ran, Chakrabarty, Krishnendu, Bhawmik, Sudipta

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2015

Language:

english

File:

PDF, 3.05 MB

english, 2015

10

[ACM Press the 35th annual conference - San Francisco, California, United States (1998.06.15-1998.06.19)] Proceedings of the 35th annual conference on Design automation conference - DAC '98 - A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Ghosh, Indradeep, Jha, Niraj K., Bhawmik, Sudipta

Year:

1998

Language:

english

File:

PDF, 131 KB

english, 1998

11

[ACM Press the 34th annual conference - Anaheim, California, United States (1997.06.09-1997.06.13)] Proceedings of the 34th annual conference on Design automation conference - DAC '97 - A hybrid algorithm for test point selection for scan-based BIST

Tsai, Huan-Chih, Lin, Chih-Jen, Bhawmik, Sudipta, Cheng, Kwang-Ting

Year:

1997

Language:

english

File:

PDF, 254 KB

english, 1997

12

[ACM Press the first international conference - Tullahoma, Tennessee, United States (1988..-..)] Proceedings of the first international conference on Industrial and engineering applications of artificial intelligence and expert systems - IEA/AIE '88 - DFTEXPERT: an expert system for design of testable VLSI circuits

Bhawmik, Sudipta, Chaudhuri, P. Pal

Year:

1988

Language:

english

File:

PDF, 758 KB

english, 1988

13

[ACM Press the 28th conference - San Francisco, California, United States (1991.06.17-1991.06.22)] Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91 - Enhanced controllability for I DDQ test sets using partial scan

Chakraborty, Tapan J., Bhawmik, Sudipta, Bencivenga, Robert, Lin, C. J.

Year:

1991

Language:

english

File:

PDF, 412 KB

english, 1991

14

[ACM Press the 36th ACM/IEEE conference - New Orleans, Louisiana, United States (1999.06.21-1999.06.25)] Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99 - Improving the test quality for scan-based BIST using a general test application scheme

Tsai, Huan-Chih, Cheng, Kwang-Tin, Bhawmik, Sudipta

Year:

1999

Language:

english

File:

PDF, 99 KB

english, 1999

15

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC

Wang, Ran, Chakrabarty, Krishnendu, Bhawmik, Sudipta

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2015

File:

PDF, 5.19 MB

2015

16

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC

Wang, Ran, Chakrabarty, Krishnendu, Bhawmik, Sudipta

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2015

Language:

english

File:

PDF, 5.19 MB

english, 2015

17

[IEEE 2013 IEEE International 3D Systems Integration Conference (3DIC) - San Francisco, CA, USA (2013.10.2-2013.10.4)] 2013 IEEE International 3D Systems Integration Conference (3DIC) - Using 3D-COSTAR for 2.5D test cost optimization

Taouil, Mottaqiallah, Hamdioui, Said, Marinissen, Erik Jan, Bhawmik, Sudipta

Year:

2013

Language:

english

File:

PDF, 514 KB

english, 2013

18

KET—A Tool for Building Expert Systems

Bhawmik, Sudipta, Athawale, P V, Palchaudhuri, Parimal

Journal:

IETE Journal of Research

Year:

1988

Language:

english

File:

PDF, 906 KB

english, 1988

19

Automated Design For Testability (DFT) Tools for VLSI Circuits

Bhawmik, Sudipta, Das, Aloke K, Palchaudhuri, Parimal

Journal:

IETE Journal of Research

Year:

1988

Language:

english

File:

PDF, 1.04 MB

english, 1988

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